In a circuit, it is often necessary to convert a signal originating in one voltage domain into a form suitable for another voltage domain. For example, if the circuit contains different components that operate in different voltage domains then it may be necessary for part of the circuit that operates in one voltage domain to interact with another part of the circuit that operates in a second voltage domain. In order to achieve this, it is possible to use a “level shifter”, which may take a signal in one voltage domain as an input and generate a corresponding signal in the second voltage domain as an output.
The voltage drop across any terminals of the components that make up the level shifter must be lower than a particular “technology limit value” (also referred to herein as a “native voltage” of those components) in order to prevent damage to the components due to overstress, which may in turn lead to reduced reliability. Consequently, it is difficult to generate a signal at a voltage that is higher than the technology limit value of the components that make up the level shifter. For example, if the level shifter is made up from CMOS components having a technology limit value of 1.8V, then it is difficult to generate a signal at a voltage of 3.3V.
A further consideration is that the level shifter may lie on the critical path of a circuit. Consequently, it is desirable for a level shifter to not introduce significant timing delays, which may cause the performance of the circuit to be adversely affected.
A problem to be solved over the prior art, therefore, is to provide an improved level shifter that takes these limitations into account.